Many types of devices employ Silicon carbide (SiC) Junction Field-Effect Transistors (JFETs). Some areas of application, to name a few, for SiC JFETs include Photo Voltaic (PV) inverters, electrical and hybrid electrical vehicles, downhole drilling, wind turbines, power factor correctors, current/voltage isolators, and the like.
The low on-state losses of SiC JFETs make it possible to either use a transistor with smaller die, thus increasing the effective current density of the system, or to use smaller and lighter cooling equipment. Moreover, the fast switching speed of these JFETs enable the system designer to use a higher switching frequency and reduce the size of the passives, or to reduce the overall switching losses in the system.
One downside to a SiC JFET is that it requires a fairly significant gate current. Indeed, most SiC JFETs require a gate current of at least 5.0 A to initially turn on the device. These devices also require a fairly significant gate current to keep the device turned on. For instance, most SiC JFETs require a hold current in the range of 0.1 A to 1.0 A. The hold current is required due to its inherent Gate-Source diode that limits the applied Gate-Source voltage. The current versus time waveform to drive a typical SiC JFET on and off is shown in FIG. 1. The first time, t1, is typically less than 200 ns and is the duration when I_PEAK is necessary to initially turn on the SiC JFET. The characteristics of a SiC JFET results in a more complex and less efficient gate drive circuit compared to that for a typical Insulated Gate Bipolar Transistor (IGBT), which requires very little current to keep it turned on.
The existing solution to drive a SiC JFET 208, as shown in FIG. 2, typically requires three drivers: 204a, 204b, and 204c. The first driver 204a produces a first output V_HOLD. The second driver 204b produces a second output V_OUTP. The third driver 204c produces a third output V_OUTN. As is typical, the SiC JFET 208 comprises a drain 212, source 216, and gate 220.
An operational state table that depicts the various combination of states for the drivers 204a, 204b, and 204c to produce the waveform of FIG. 1 is shown below.
TABLE 1State Table for driving solution of FIGS. 1 and 2S1S2S3SiC JFET on (t1)OnOnOffSiC JFET on (t2)OnOffOffSiC JFET off (t3)OffOffOn
V_HOLD, driven between V_CC2 (often approximately +15V) and V_EE2 (often approximately −15V), is used to provide the holding current I_HOLD to maintain the SiC JFET 208 in its on state during t1 and t2; V_OUTP, driven between V_CC2 (often approximately +15V) and V_E (often approximately 0V), is used to turn on the HD PMOS 224 switch for the duration of t1 to provide the large initial current I_PEAK; V_OUTN, supplied between V_E (often approximately 0V) and V_EE2 (often approximately −15V), is to drive the LD_NMOS 228 to turn the SiC JFET off during t3.
R_3 and R_4 are provided to limit the peak turn-on and turn-off current at the gate 220 of SiC JFET 208. R_HOLD is used to set the holding current, I_HOLD.
The existing solution as depicted in FIGS. 1 and 2 has several disadvantages. First of all, the existing solution is relatively complex. It requires three distinct drivers to operate. A master control signal has to be translated by driver logic into three separate signals S1, S2, and S3, and the on-off timing control among these three signals is essential to prevent any current shoot-through event. The existing solution also requires a t1 timer for S2 to limit the turn-on duration of V_OUTP.
Another significant disadvantage to the existing solution is power inefficiency. I_HOLD needs to be conducting whenever the SiC JFET 208 is on. To minimize the power consumption, V_CC2, the supply to the first driver 204a, needs to be kept as low as just slightly above the threshold voltage of the SiC JFET 208. However, high voltage at V_CC2 is needed for the first driver 204a to develop the high current I_PEAK. The two competing requirements on V_CC2 means that I_HOLD is driven at a voltage higher than its own need. The architecture is inherently not power efficient, unless there is a dedicated voltage source to supply the first driver 204a, but a third power supply means power inefficiency in another way.